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CD player, as an indispensable audio sản phẩm in the 20th century, has a transport and a DAC in one box. But, vì chưng you ever wonder how is the information for transport connected to lớn the DAC inside of a CD player? The Inter-IC Sound(I2S) Bus is the key!

In this blog, I will cover the following topics:

Introduction to lớn Inter-IC Sound(I2S)Inter-IC Sound(I2S) v.s. Inter-Integrated Circuit(I2C)What is I2S?I2S Operation ModesI2S with Arduino & Raspberry Pi

Introduction lớn Inter-IC Sound(I2S)

Similar lớn the CD player, lots of digital audio systems need the (V)LSI ICs for processing:

DAC and ADCDigital signal processorsError correction for CD và digital recordingDigital filtersDigital input / output interface

Standardized communication structures are critical for manufacturers in order to increase the flexibility of the system. I2S is designed for this purpose.

Inter-IC Sound(I2S) or Integrated Interchip Sound is a digital audio serial bus interface transmission standard defined by Philips in February 1986 (revised June 1996). It aims lớn transmit digital audio data between the internal devices of the system, such as CODEC, DSP, digital input/output interface, DAC, ADC and digital filter.

Be careful not to lớn confuse I2S with the other Phillips Semiconductor protocol, Inter-Integrated Circuit(I2C), which was released in 1982.Bạn đã xem: I2s interface là gì

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Inter-IC Sound(I2S) v.s. Inter-Integrated Circuit(I2C)

Inter-IC Sound(I2S)

Used lớn connect digital audio devices. It is an electrical bus interface standard as well. Low jitter connection since the data and clock signal transmit separately. Support full-duplex / half-duplexSupport master/slave modeSupport multiple channels, since the variant of I2S supports multi-channel time-division multiplexingDelivers fully digital audio signal chain.It eliminates ADC/DACs & pre-amplifier usually found in the traditional audio chainNo issue with synchronization with the use of master clock

Inter-Integrated Circuit(I2C)


I2C includes electrical & timing specifications, & an associated bus protocol. Low-speed & two-wire serial data connection bus.Bi-directional data transfer. Used for signals transmission between ICs on the same PCB.Two lines only between multiple masters and multiple slaves, Serial Dara(SDA) & Serial Clock(SCL).Synchronous communication, it has a global clock signal between masters & slaves.Support different data rates, e.g. 100Kbps, 400Kbps, 1Mbps, and 3.4Mbps.Unique start and stop condition. Start and stop bits as well as ACK bit is used for every 8 bits of data transfer.No fixed length to lớn transfer

In Summary, the I2C bus is used to lớn connect the microcontroller & its peripheral devices while the I2S bus focuses on the audio data transmission between digital audio devices.

But, what is I2S và what does it actually do?

What is I2S?

ref. I2S Configurations

The bus has only to handle the audio signal, while the other signals, such as sub-coding & control, are transferred separately. To minimize the number of pins, there are three lines defined in the I2S bus:

word select line (WS)continuous serial clock line (SCK)serial data line (SD)

The device generating SCK & WS is the master. However, it is hard khổng lồ define the master for the system with several transmitters & receivers. In this case, a system master is defined as controlling the flow of digital audio data between various ICs. Hence, transmitters need to lớn generate data under the control of an external clock và act as a slave.

Bạn đang xem: I2s interface là gì


I2S interface timing diagram. Ref. I2S bus specification by Phillips

word select line

A word select line is the channel selection signal, indicating the channel selected by the transmitter.

WS = 0, channel 1 (left)WS = 1, channel 2 (right)

WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need lớn be symmetrical.

In the slave, the signal is latched on the leading edge of the clock signal. The WS line changes one clock period before the MSB is transmitted allows the slave transmitter to lớn derive synchronous timing of the serial data that will be mix up for transmission. Furthermore, it enables the receiver to lớn store the previous word and clear the input đầu vào for the next word.

Clock line

Officially “continuous serial clock (SCK)”, typically written “bit clock (BCLK)”, is the synchronization signal in the module which is provided externally in slave mode và internally generated in master mode.

SCK = Sampling frequency (e.g. 48kHz, 44.1kHz, etc) * word length (16bit, 24bit, 32bit) * 2 (left and right channels)

Take propagation delays between the master clock và the data and/or word select signals into account, the total delay is the sum of:the delay between the external(master) clock and the slave’s internal clock; andthe delay between the internal clock và the data and/or WS signals.

Data line

The serial data is transmitted in two’s complement with the MSB first. The MSB is transmitted because of different word lengths between transmitter và receiver.

If the system word length is greater than the transmitter word length, the word is truncated (LSBs are set to ‘0’) for data transmission. If the receiver is sent more bits than its word length, the bits after the LSB are ignored. If the receiver is sent fewer bits than its word length, the missing bits are set to lớn zero internally.

The MSB has a fixed position, whereas the position of the LSB depends on the word length. The sender always sends the MSB of the next word one clock period after the WS changes.

Serial data sent by the transmitter may be synchronized with either falling or rising edge of the clock signal. However, the serial data must be latched into the receiver on the rising edge of the clock signal.

I2S Operation Modes

Phillips Standard


Phillips Standard is a special case of left-justified, which is delayed by a change of one clock bit from the standard left justified standard. The data MSB of both left và right channels are valid after the second SCK / BCLK rising edge after WS changes.

Left Justified Standard


Left Justified Standard is not widely used, it is not delayed by one clock relative to BCLK. The MSB of both channels is valid after the first rising edge of SCK / BCLK after WS changes.

Right Justified Standard


Right Justified Standard, also called Japanese format, Electronic Industries Association of Japan(EIAJ) or SONY format. The LSB of the left channel is valid at the rising edge of SCK / BCLK before the falling edge of WS, while the LSB of the right channel is valid at the rising edge of SCK / BCLK before the rising edge of WS.

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Compared to lớn Left Justified Standard, the disadvantage of Right Justified Standard is that the receiving device must know the word length of the data lớn be transmitted in advance.

Please be careful, for Right Justified Standard và Left Justified Standard:

WS = 1, channel 1 (left)WS = 0, channel 2 (right)

It is opposite to lớn the Phillips Standard!

I2S with Arduino and Raspberry Pi

with Arduino

With the use of I2S bus, a low jitter audio data transmission between digital devices is achieved. Now, it’s time khổng lồ build your real-time MIDI music player with this I2S protocol! In Seeed, a music shield is designed for this purpose which is compatible with Arduino, Seeeduino, Seeeduino Mega, and Arduino Mega.

with Raspberry Pi

You are a fan of Raspberry Pi? Don’t worry, there is a perfect suite for you. ReSpeaker 4-Mic Array for Raspberry Pi is a 4 microphone expansion board for Raspberry Pi designed for AI và voice applications. This means that you can build a more powerful và flexible voice product that integrates Amazon Alexa Voice Service, Google Assistant, and so on.